A low package resistance Rds-on and good performance is often desirable for semiconductor devices. This is particularly the case for metal oxide silicon field effect transistor (MOSFET) devices, especially vertical conduction power MOSFET devices having a gate and source electrode on one surface and a drain electrode on the opposite surface. It is also generally desirable to have simple, quick and efficient methods of packaging semiconductor devices. Thus, numerous packaging concepts and methods have been developed in the prior art.
While silicon process technology has advanced significantly in the past decade, for the most part, the same decades-old package technology continues as the primary packaging means. Epoxy or solder die attach along with aluminum or gold wire bonding to a lead frame is still the preferred semiconductor package methodology. Advances in semiconductor processing technology, however, have made parasitics (e.g., resistances, capacitances and inductances) associated with conventional packages more of a performance limiting factor. In the case of conventional flip chip technology, among other shortcomings, heat dissipation is essentially governed by the die size and connection to the back side of the die is not easily facilitated (often requiring a bond wire connection). These limitations (poor heat dissipation and resistive contact to back side) become quite significant in high current applications such as power switching devices.
U.S. Pat. No. 6,767,820 discloses a chip scale packaging of semiconductor MOS-gated device. The source side of a MOS-gated device wafer is covered with a passivation layer, preferably a photosensitive liquid epoxy, or a silicon nitride layer, or the like. The material is then dried and the coated wafer is exposed using standard photolithographic techniques to image the wafer and openings are formed in the passivation layer to produce a plurality of spaced exposed surface areas of the underlying source metal and a similar opening to expose the underlying gate electrode of each die on the wafer. The openings in the passivation layer are typically made through to a conventional underlying solderable top metal such as a titanium/tungsten/nickel/silver metal. After the openings are formed, the wafer is then sawn or otherwise singulated into individual die. The individual die are then placed source-side down and a U-shaped or cup shaped, partially plated drain clip is connected to the solderable drain side of the die, using a conductive epoxy or solder, or the like to bond the drain clip to the bottom drain electrode of the die. The bottoms of the legs of the drain clip are coplanar with the source-side surface (that is the tops of the contact projections) of the die. However, the U-shaped clip is usually made of a copper alloy with at least partially plated silver surfaces and is actually very thin. The clip, therefore, tends to be expensive. In addition, different U-shaped clips are needed for different die sizes or larger U-shaped clips are used for smaller die, which takes a lot space on the PC board.
US publication number 2003/0052405 discloses a vertical power MOSFET device having the source electrode and the gate electrode are connected to the lead frames by bonding material such as solder, and the drain electrode underlying the entire bottom surface of the chip is directly connected to the mounting substrate. The vertical MOSFET device is located upside down such that the drain electrode formed on the bottom surface of the silicon substrate will be connected to the lead frame above it whereas the gate electrode and the source electrode will be exposed to the bottom of the device. The MOSFET device is sealed by a resin, such as epoxy or silicone, such that the MOSFET device and an inner part of the lead frame are covered. On the bottom surface of the MOSFET device, the surface of the resin is approximately flush with surfaces of the lead frame and the drain electrodes. That is, on the bottom surface of the semiconductor device, the bottom surface of outer lead portions of the lead frame and bottom surfaces of drain electrodes are exposed for connection to a conductor land (mount surface) of the mounting substrate. Then the perimeter of these drain electrodes is covered by the resin.
U.S. Pat. No. 6,133,634 discloses a flip chip package having a power MOSFET device including a drain terminal, a source terminal and a gate terminal. The drain terminal connects to a conductive carrier and an outer array of solder balls. The source terminal and gate terminal connect to an inner array of solder balls. The conductive carrier and the outer array of solder balls provide electrical connection between the printed circuit board and the drain terminal.
U.S. Pat. No. 6,469,384 discloses a method of packaging semiconductor devices, such as MOSFET device, which does not require a molded body. The MOSFET device is coupled to a substrate such that the source and gate regions of the die are coupled to the substrate. The MOSFET device is placed on a printed circuit board (PCB) and the surface of the die is coupled directly to the PCB with solder paste or suitable electrically conductive interconnect, and thus serves as the drain connection. The surface of the die coupled to the substrate comprises the gate region and the source region of the die. Thus, the solder ball in the gate region of the substrate serves to couple the gate region of the die to the PCB while the remaining solder balls couple the source region of the die through the substrate to the PCB.
The preceding prior art package design for vertical power MOSFET devices can only provide the electrical interconnection for source, gate and drain for individual MOSFET at a time after singulation, which is expensive and time consuming. In addition the available space of the die is reduced. It would be desirable to produce a package design and process for its manufacture which permits batch handling with reduced equipment on the production line and lower costs.
It is within this context that embodiments of the present invention arise.